我要评论一、实验要求
实现fpga与eeprom的通信，要求fpga对eeprom实现先“写”后“读”，读出的值给uart发送端并显示到电脑上，按下按键1让fpga对eeprom写入数据；按下按键2让fpga读出对eeprom写入过的数据。
二、信号流向图
三、程序设计
（1）按键消抖模块
`timescale 1ns / 1ps
module key(
input sys_clk ,
input rst_n ,
(* mark_debug="true" *)input key1 ,
(* mark_debug="true" *)input key2 ,
(* mark_debug="true" *)output key_flag_1 ,
(* mark_debug="true" *)output key_flag_2
);
parameter delay = 20'd1_000_000 ; //20ms=20_000_000 20_000_000/20 == 10_000_00
reg[19:0] cnt1 ;
reg[19:0] cnt2 ;
always@(posedge sys_clk )
if(!rst_n)
cnt1 <= 0 ;
else if ( key1 == 0 )begin
if ( cnt1 == delay -1 )
cnt1 <= cnt1 ;
else
cnt1 <= cnt1 +1 ;
end
else
cnt1 <= 0 ;
always@(posedge sys_clk )
if(!rst_n)
cnt2 <= 0 ;
else if ( key2 == 0 )begin
if ( cnt2 == delay -1 )
cnt2 <= cnt2 ;
else
cnt2 <= cnt2 +1 ;
end
else
cnt2 <= 0 ;
assign key_flag_1 = ( cnt1 == delay -2 )?1:0 ;
assign key_flag_2 = ( cnt2 == delay -2 )?1:0 ;
endmodule
（2）数据产生模块
`timescale 1ns / 1ps
module data_generate(
input sys_clk ,
input rst_n ,
input iic_end ,
input key_flag_1 ,
input key_flag_2 ,
(* mark_debug="true" *)output reg wr_en ,
(* mark_debug="true" *)output reg rd_en ,
(* mark_debug="true" *)output reg iic_start //按键消抖后延迟1000个时钟周期
);
always@(posedge sys_clk )
if(!rst_n)
wr_en <= 0 ;
else if ( key_flag_1 )
wr_en <= 1 ;
else if ( iic_end )
wr_en <= 0 ;
else
wr_en <= wr_en ;
always@(posedge sys_clk )
if(!rst_n)
rd_en <= 0 ;
else if ( key_flag_2 )
rd_en <= 1 ;
else if ( iic_end )
rd_en <= 0 ;
else
rd_en <= rd_en ;
///cnt
parameter time_count = 10'd1000 ;
(* mark_debug="true" *)reg[9:0] cnt ;
always@(posedge sys_clk )
if(!rst_n )
cnt <= 0 ;
else if ( wr_en || rd_en )begin
if ( cnt == time_count -1 )
cnt <= cnt ;
else
cnt <= cnt +1 ;
end
else
cnt <= 0 ;
iic_start
always@(posedge sys_clk )
if(!rst_n)
iic_start <= 0 ;
else if ( cnt == time_count -2 )
iic_start <= 1 ;
else
iic_start <= 0 ;
endmodule
（3）iic模块
`timescale 1ns / 1ps
module iic_2
#(
parameter sysclk = 50_000_000 ,
iic_clk = 400_000 ,
device_id = 7'b1010_000
)
(
input sysclk ,
input rst_n ,
input [7:0] data_in ,
input [7:0] addr ,
input iic_start , 尖峰脉冲
input wr_en , ///按键1按下触发
input rd_en , ///按键2按下触发
(* mark_debug="true" *)output tx_start ,
(* mark_debug="true" *)output reg [7:0] rd_data ,
(* mark_debug="true" *)output reg scl ,
(* mark_debug="true" *)inout sda ,
(* mark_debug="true" *)output iic_end /尖峰脉冲
);
localparam delay = sysclk/iic_clk ;
//三态门
wire sda_en ; ///sda先作为输出时候的使能信号线
wire sda_in ; 从机给主机的数据线
reg sda_out ; /主机给从机的数据线
assign sda = (sda_en == 1) ? sda_out : 1'bz ;
assign sda_in = sda;
状态机
localparam idle = 4'd0 ,
start1 = 4'd1 ,
send_device_w = 4'd2 ,
ack1 = 4'd3 ,
send_addr_w = 4'd4 ,
ack2 = 4'd5 ,
send_data_w = 4'd6 ,
ack3 = 4'd7 ,
stop = 4'd8 ,
start2 = 4'd9 ,
send_device_r = 4'd10 ,
ack4 = 4'd11 ,
read_data = 4'd12 ,
noack = 4'd13 ;
(* mark_debug="true" *)reg [3:0] cur_state ;
reg [3:0] next_state ;
(* mark_debug="true" *)reg [7:0] cnt ;
(* mark_debug="true" *)reg [2:0] cnt_bit ;
(* mark_debug="true" *)reg ack_flag ;
assign sda_en = (cur_state == ack1 || cur_state == ack2 ||
cur_state == ack3 || cur_state == ack4 || cur_state == read_data) ? 0 : 1;
assign tx_start = (cur_state == read_data && cnt_bit == 7 && cnt == delay - 1) ? 1 : 0;
assign iic_end = (cur_state == stop && cnt == delay - 1) ? 1 : 0;
/state1
always@(posedge sysclk)
if(!rst_n)
cur_state <= idle;
else
cur_state <= next_state;
/state2
always@(*)
case(cur_state)
idle : begin
if(iic_start == 1)
next_state = start1;
else
next_state = cur_state;
end
start1 :begin
if(cnt == delay - 1)
next_state = send_device_w;
else
next_state = cur_state;
end
send_device_w :begin
if(cnt == delay - 1 && cnt_bit == 7)
next_state = ack1;
else
next_state = cur_state;
end
ack1 :begin
if(cnt == delay - 1 && ack_flag == 0) /应答有效
next_state = send_addr_w;
else if(cnt == delay - 1 && ack_flag == 1) /应答无效
next_state = idle;
else
next_state = cur_state;
end
send_addr_w :begin
if(cnt == delay - 1 && cnt_bit == 7)
next_state = ack2;
else
next_state = cur_state;
end
ack2 :begin
if(cnt == delay - 1 && ack_flag == 0 && wr_en) /应答有效
next_state = send_data_w;
else if(cnt == delay - 1 && ack_flag == 0 && rd_en) /应答有效
next_state = start2;
else if(cnt == delay - 1 && ack_flag == 1) /应答无效
next_state = idle;
else
next_state = cur_state;
end
send_data_w :begin
if(cnt == delay - 1 && cnt_bit == 7)
next_state = ack3;
else
next_state = cur_state;
end
ack3 :begin
if(cnt == delay - 1 && ack_flag == 0) /应答有效
next_state = stop;
else if(cnt == delay - 1 && ack_flag == 1) /应答无效
next_state = idle;
else
next_state = cur_state;
end
stop :begin
if(cnt == delay - 1)
next_state = idle;
else
next_state = cur_state;
end
start2 : begin
if(cnt == delay - 1)
next_state = send_device_r;
else
next_state = cur_state;
end
send_device_r :begin
if(cnt == delay - 1 && cnt_bit == 7)
next_state = ack4;
else
next_state = cur_state;
end
ack4 :begin
if(cnt == delay - 1 && ack_flag == 0) /应答有效
next_state = read_data;
else if(cnt == delay - 1 && ack_flag == 1) /应答无效
next_state = idle;
else
next_state = cur_state;
end
read_data :begin
if(cnt == delay - 1 && cnt_bit == 7)
next_state = noack;
else
next_state = cur_state;
end
noack :begin
if(cnt == delay - 1)
next_state = stop;
else
next_state = cur_state;
end
default:next_state = idle;
endcase
state3
always@(posedge sysclk)
if(!rst_n)begin
cnt <= 0;
cnt_bit <= 0;
sda_out <= 1; 空闲为1
scl <= 1;空闲为1
ack_flag <= 1; 无效应答
rd_data <= 0;
end
else
case(cur_state)
idle :begin
rd_data <= 0;
cnt <= 0;
cnt_bit <= 0;
sda_out <= 1;
scl <= 1;
ack_flag <= 1;
end
start1 :begin
ack_flag <= 1;
if(cnt >= delay*3/4 - 1)
scl <= 0;
else
scl <= 1;
if(cnt >= delay/2 - 1)
sda_out <= 0;
else
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
send_device_w :begin 先发最高位 0-7 0-6 7
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
if(cnt_bit >=0 && cnt_bit < 7)
sda_out <= device_id[6-cnt_bit];
else /cnt_bit == 7
sda_out <= 0; //写标志位
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
if(cnt == delay - 1)
cnt_bit <= cnt_bit + 1;
else
cnt_bit <= cnt_bit;
end
ack1 :begin /从机给主机数据
if(cnt == delay/2 - 1)
ack_flag <= sda_in ;
else
ack_flag <= ack_flag;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
send_addr_w :begin
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= addr[7-cnt_bit];
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
if(cnt == delay - 1)
cnt_bit <= cnt_bit + 1;
else
cnt_bit <= cnt_bit;
end
ack2 :begin
if(cnt == delay/2 - 1)
ack_flag <= sda_in ;
else
ack_flag <= ack_flag;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
send_data_w :begin
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= data_in[7-cnt_bit];
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
if(cnt == delay - 1)
cnt_bit <= cnt_bit + 1;
else
cnt_bit <= cnt_bit;
end
ack3 :begin
if(cnt == delay/2 - 1)
ack_flag <= sda_in ;
else
ack_flag <= ack_flag;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
stop :begin
ack_flag <= 1;
if(cnt >= delay/4 - 1)
scl <= 1;
else
scl <= 0;
if(cnt >= delay/2 - 1)
sda_out <= 1;
else
sda_out <= 0;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
start2 :begin
ack_flag <= 1;
if(cnt >= delay*3/4 - 1)
scl <= 0;
else
scl <= 1;
if(cnt >= delay/2 - 1)
sda_out <= 0;
else
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
send_device_r :begin
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
if(cnt_bit >=0 && cnt_bit < 7)
sda_out <= device_id[6-cnt_bit];
else /cnt_bit == 7
sda_out <= 1; //读标志位
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
if(cnt == delay - 1)
cnt_bit <= cnt_bit + 1;
else
cnt_bit <= cnt_bit;
end
ack4 :begin
if(cnt == delay/2 - 1)
ack_flag <= sda_in ;
else
ack_flag <= ack_flag;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
read_data :begin
if(cnt == delay/2 - 1)
// rd_data[7-cnt_bit] <= sda_in; /法1
rd_data <= {rd_data[6:0],sda_in}; 法2
else
rd_data <= rd_data;
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
if(cnt == delay - 1)
cnt_bit <= cnt_bit + 1;
else
cnt_bit <= cnt_bit;
end
noack :begin
ack_flag <= 1;
if(cnt >= delay/4 - 1 && cnt <= delay*3/4 - 1)
scl <= 1;
else
scl <= 0;
sda_out <= 1;
cnt_bit <= 0;
if(cnt == delay - 1)
cnt <= 0;
else
cnt <= cnt + 1;
end
endcase
endmodule
（4）发送端模块
`timescale 1ns / 1ps
module uart_tx(
input sys_clk ,
input rst_n ,
input tx_start ,
(* mark_debug="true" *) input [7:0] rd_data ,
(* mark_debug="true" *)output reg tx_data ,
output reg tx_done
);
parameter sysclk = 50_000_000 ;
parameter baud = 115200 ;
parameter count = sysclk/baud;
parameter mid = count/2 ;
//start_flag
reg tx_reg1 ;
reg tx_reg2 ;
(* mark_debug="true" *)wire start_flag ;
always@(posedge sys_clk )
if(!rst_n)begin
tx_reg1 <= 0 ;
tx_reg2 <= 0 ;
end
else
begin
tx_reg1 <= tx_start ;
tx_reg2 <= tx_reg1 ;
end
assign start_flag = tx_reg1 & ~tx_reg2 ;
//tx_flag
(* mark_debug="true" *) reg tx_flag ;
(* mark_debug="true" *) reg [9:0] cnt ;
(* mark_debug="true" *) reg [4:0] cnt_bit ; //0 12345678 9 10
always@(posedge sys_clk )
if(!rst_n)
tx_flag <= 0 ;
else if ( start_flag )
tx_flag <= 1 ;
else if ( cnt == count -1 && cnt_bit == 10 )
tx_flag <= 0 ;
else
tx_flag <= tx_flag ;
//cnt
always@(posedge sys_clk )
if(!rst_n)
cnt <= 0 ;
else if ( tx_flag )begin
if ( cnt == count -1 )
cnt <= 0 ;
else
cnt <= cnt +1 ;
end
else
cnt <= 0 ;
//cnt_bit
always@(posedge sys_clk )
if(!rst_n)
cnt_bit <= 0 ;
else if ( tx_flag )begin
if ( cnt == count -1 )begin
if ( cnt_bit == 10 )
cnt_bit <= 0 ;
else
cnt_bit <= cnt_bit +1 ;
end
else
cnt_bit <= cnt_bit ;
end
else
cnt_bit <= 0 ;
//寄存rd_data rd_data随着cur_state变为stop后清零，在uart_tx模块
//中，cnt_bit == 0 的时候可以捕捉到数据
(* mark_debug="true" *) reg[7:0] data_reg ;
always@(posedge sys_clk )
if(!rst_n)
data_reg <= 0 ;
else if ( tx_flag )begin
if ( cnt_bit == 0 && cnt == mid -1 )
data_reg <= rd_data ;
else
data_reg <= data_reg ;
end
else
data_reg <= data_reg ;
//tx_data
parameter mode_check = 0 ;
always@(posedge sys_clk )
if(!rst_n) //cnt_bit: 0 12345678 9 10
tx_data <= 0 ; //rd_data: 01234567
else if ( tx_flag )begin
if ( cnt_bit > 0 && cnt_bit <9 )
tx_data <= data_reg [ cnt_bit -1 ] ;
else if ( cnt_bit == 0 )
tx_data <= 0 ;
else if ( cnt_bit == 10 )
tx_data <= 1 ;
else if ( cnt_bit == 9 )
tx_data <= (mode_check == 0 )? ^rd_data : ~^rd_data ;
else
tx_data <= tx_data ;
end
else
tx_data <= 1 ;
//tx_done
always@(posedge sys_clk )
if(!rst_n)
tx_done <= 0 ;
else if ( tx_flag )begin
if ( cnt == count -1 && cnt_bit == 10 )
tx_done <= 1 ;
else
tx_done <= 0 ;
end
else
tx_done <= 0 ;
endmodule
（5）top模块
`timescale 1ns / 1ps
module iic_top(
input sys_clk ,
input rst_n ,
input key1 ,
input key2 ,
output tx_data ,
output scl ,
inout sda
);
key
wire key_flag_1 ;
wire key_flag_2 ;
key key_u1(
. sys_clk (sys_clk ) ,
. rst_n (rst_n ) ,
. key1 (key1 ) ,
. key2 (key2 ) ,
. key_flag_1 (key_flag_1 ) ,
. key_flag_2 (key_flag_2 )
);
///data_generate
wire iic_end ;
wire wr_en ;
wire rd_en ;
wire iic_start ;
data_generate data_generate_u1(
. sys_clk (sys_clk ) ,
. rst_n (rst_n ) ,
. iic_end (iic_end ) ,
. key_flag_1 (key_flag_1) ,
. key_flag_2 (key_flag_2) ,
. wr_en (wr_en ) ,
. rd_en (rd_en ) ,
. iic_start (iic_start ) //按键消抖后延迟1000个时钟周期
);
iic
wire tx_start ;
wire [7:0] rd_data ;
iic_2
#(
. sysclk (50_000_000 ) ,
. iic_clk (400_000 ) ,
. device_id (7'b1010_000)
)
iic_2_u1(
. sysclk (sys_clk) ,
. rst_n (rst_n ) ,
. data_in (8'h45) ,
. addr (8'h12) ,
. iic_start (iic_start) , 尖峰脉冲
. wr_en (wr_en ) , ///按键1按下触发
. rd_en (rd_en ) , ///按键2按下触发
. tx_start (tx_start) ,
. rd_data (rd_data ) ,
. scl (scl ) ,
. sda (sda ) ,
. iic_end (iic_end ) /尖峰脉冲
);
///uart_tx
wire tx_done ;
uart_tx uart_tx_u1(
. sys_clk (sys_clk ) ,
. rst_n (rst_n ) ,
. tx_start (tx_start) ,
. rd_data (rd_data ) ,
. tx_data (tx_data ) ,
. tx_done (tx_done )
);
endmodule
（6）绑定管脚
set_property iostandard lvcmos33 [get_ports key1]
set_property iostandard lvcmos33 [get_ports key2]
set_property iostandard lvcmos33 [get_ports rst_n]
set_property iostandard lvcmos33 [get_ports scl]
set_property iostandard lvcmos33 [get_ports sda]
set_property iostandard lvcmos33 [get_ports sys_clk]
set_property iostandard lvcmos33 [get_ports tx_data]
set_property package_pin m19 [get_ports key1]
set_property package_pin m20 [get_ports key2]
set_property package_pin p15 [get_ports rst_n]
set_property package_pin f19 [get_ports scl]
set_property package_pin f20 [get_ports sda]
set_property package_pin k17 [get_ports sys_clk]
set_property package_pin u18 [get_ports tx_data]
四、set up debug使用步骤
然后点set up debug
xdc文件变成这样就是保存成功了
set_property iostandard lvcmos33 [get_ports key1]
set_property iostandard lvcmos33 [get_ports key2]
set_property iostandard lvcmos33 [get_ports rst_n]
set_property iostandard lvcmos33 [get_ports scl]
set_property iostandard lvcmos33 [get_ports sda]
set_property iostandard lvcmos33 [get_ports sys_clk]
set_property iostandard lvcmos33 [get_ports tx_data]
set_property package_pin m19 [get_ports key1]
set_property package_pin m20 [get_ports key2]
set_property package_pin p15 [get_ports rst_n]
set_property package_pin f19 [get_ports scl]
set_property package_pin f20 [get_ports sda]
set_property package_pin k17 [get_ports sys_clk]
set_property package_pin u18 [get_ports tx_data]
create_debug_core u_ila_0 ila
set_property all_probe_same_mu true [get_debug_cores u_ila_0]
set_property all_probe_same_mu_cnt 1 [get_debug_cores u_ila_0]
set_property c_adv_trigger false [get_debug_cores u_ila_0]
set_property c_data_depth 4096 [get_debug_cores u_ila_0]
set_property c_en_strg_qual false [get_debug_cores u_ila_0]
set_property c_input_pipe_stages 0 [get_debug_cores u_ila_0]
set_property c_trigin_en false [get_debug_cores u_ila_0]
set_property c_trigout_en false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list sys_clk_ibuf_bufg]]
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {iic_2_u1/cnt[0]} {iic_2_u1/cnt[1]} {iic_2_u1/cnt[2]} {iic_2_u1/cnt[3]} {iic_2_u1/cnt[4]} {iic_2_u1/cnt[5]} {iic_2_u1/cnt[6]} {iic_2_u1/cnt[7]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe1]
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {iic_2_u1/cnt_bit[0]} {iic_2_u1/cnt_bit[1]} {iic_2_u1/cnt_bit[2]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe2]
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {iic_2_u1/cur_state[0]} {iic_2_u1/cur_state[1]} {iic_2_u1/cur_state[2]} {iic_2_u1/cur_state[3]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe3]
set_property port_width 10 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {data_generate_u1/cnt[0]} {data_generate_u1/cnt[1]} {data_generate_u1/cnt[2]} {data_generate_u1/cnt[3]} {data_generate_u1/cnt[4]} {data_generate_u1/cnt[5]} {data_generate_u1/cnt[6]} {data_generate_u1/cnt[7]} {data_generate_u1/cnt[8]} {data_generate_u1/cnt[9]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe4]
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {uart_tx_u1/rd_data[0]} {uart_tx_u1/rd_data[1]} {uart_tx_u1/rd_data[2]} {uart_tx_u1/rd_data[3]} {uart_tx_u1/rd_data[4]} {uart_tx_u1/rd_data[5]} {uart_tx_u1/rd_data[6]} {uart_tx_u1/rd_data[7]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe5]
set_property port_width 8 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {iic_2_u1/rd_data[0]} {iic_2_u1/rd_data[1]} {iic_2_u1/rd_data[2]} {iic_2_u1/rd_data[3]} {iic_2_u1/rd_data[4]} {iic_2_u1/rd_data[5]} {iic_2_u1/rd_data[6]} {iic_2_u1/rd_data[7]}]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list iic_2_u1/ack_flag]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list iic_2_u1/iic_end]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list data_generate_u1/iic_start]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list key_u1/key1]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list key_u1/key2]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list key_u1/key_flag_1]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list key_u1/key_flag_2]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list data_generate_u1/rd_en]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list iic_2_u1/scl]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list iic_2_u1/sda_ibuf]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list iic_2_u1/sda_obuf]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list uart_tx_u1/tx_data]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list iic_2_u1/tx_start]]
create_debug_port u_ila_0 probe
set_property probe_type data_and_trigger [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list data_generate_u1/wr_en]]
set_property c_clk_input_freq_hz 300000000 [get_debug_cores dbg_hub]
set_property c_enable_clk_divider false [get_debug_cores dbg_hub]
set_property c_user_scan_chain 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets sys_clk_ibuf_bufg]
"4"对应后面几个cnt_bit
五、实验结果
按下控制“写”的按键，再按下“读”的按键后，pc端返回45
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